/****************************************************************************
 *			SRLOS Team All Right Reserved									*
 *																			*
 *breaf: this file is the main program of srlos boot						*
 *autor: bloceanc															*
 *e-mail: bloceanc@gmail.com												*
 *																			*
 *																			*
 ****************************************************************************/
#ifndef _BOOT_H
#define	_BOOT_H

/* -------------------------------------------------------------------------------------
 * define commons macros
 * ------------------------------------------------------------------------------------*/
#define	NAND_FLASH_BLOCK_SIZE			512									// nand flash bock size
#define	NAND_FLASH_BLOCK_MASK			(NAND_FLASH_BLOCK_SIZE -1)
#define	NAND_FLASH_KERNEL_ADDRESS		0x00001000							// save kernel at 4K in nand flash
#define	NAND_FLASH_KERNEL_SIZE			0x00100000							// kernel size in nand flash, 1MB

#define	SDRAM_START_ADDRESS				0x30000000							// SDRAM start adddress
#define	SDRAM_END_ADDRESS				0x33ffffff							// 2440 64M SDRAM

// OS MMU table address and record count macros
#define	MMU_VIRTUAL_ADDR_BOOTLOADER		0x00000000						// bootloader start virtual address
#define	MMU_VIRTUAL_ADDR_SLPT			0x00001000						// SLPT start virtual address
#define	MMU_VIRTUAL_ADDR_RESV			0x00101000						// Reserved for FLPT reside 16KB
#define	MMU_VIRTUAL_ADDR_FLPT			0x00104000						// FLPT start virtual address

// Kernel loaded address(VA) warnning:this value must be the same as ldr pc operator in boot.s file!
#define	MMU_VIRTUAL_ADDR_KERNEL			0x00105000

#define	MMU_OS_BOOTER_SIZE				0x00001000						// boot sector size (4KB)
#define	MMU_OS_FLPT_RCD_COUNT_MEM		0x200							// OS FLPT Record count  512.(for 512M VA)
#define	MMU_OS_SLPT_RCD_COUNT_MEM		0x20000							// OS SLPT Record count  512 * 256(for 512M VA)
#define	MMU_OS_FLPT_RCD_COUNT_IO		0x200							// OS IO Mapping FLPT Record count 512M
#define	MMU_OS_SLPT_RCD_COUNT_IO		0x20000							// OS IO Mapping SLPT Record count 512M

#define	MMU_PHYSICAL_ADDR_BOOTLOADER	(MMU_VIRTUAL_ADDR_BOOTLOADER + SDRAM_START_ADDRESS)
#define	MMU_PHYSICAL_ADDR_SLPT_MEM		(MMU_VIRTUAL_ADDR_SLPT + SDRAM_START_ADDRESS)
#define	MMU_PHYSICAL_ADDR_SLPT_IO		(MMU_VIRTUAL_ADDR_SLPT + (MMU_OS_SLPT_RCD_COUNT_MEM << 2) + SDRAM_START_ADDRESS)
#define	MMU_PHYSICAL_ADDR_FLPT_MEM		(MMU_VIRTUAL_ADDR_FLPT + SDRAM_START_ADDRESS)
#define	MMU_PHYSCIAL_ADDR_FLPT_IO		(MMU_VIRTUAL_ADDR_FLPT + (MMU_OS_FLPT_RCD_COUNT_MEM << 2) + SDRAM_START_ADDRESS)
#define	MMU_PHYSICAL_ADDR_KERNEL		(MMU_VIRTUAL_ADDR_KERNEL + SDRAM_START_ADDRESS)

// IO Mapping Address Infomation
#define	MMU_PHYSICAL_ADDR_IOMAPPING		0x48000000						// this value + 512M must cover all IO address space!
#define	MMU_VIRTUAL_ADDR_IOMAPPING		0x20000000						// IO mapped virtual address

/* -------------------------------------------------------------------------------------
 * define the registers , MMU is disabled, and those addresses are physical addresses 
 * ------------------------------------------------------------------------------------*/

// PLL configure registers
#define	R_MPLLCON	(*((volatile unsigned long *)0x4c000004))		// MPLL configure register
#define	R_UPLLCON	(*((volatile unsigned long *)0x4c000008))		// UPLL configure register

// CLOCK registers
#define	R_CLKDIVN	(*((volatile unsigned long *)0x4c000014))		// CLOCK DIVIDER CONTROL REGISTER

// BUS WIDTH & WAIT CONTROL REGISTER (BWSCON)
#define	R_BWSCON	(*((volatile unsigned long *)0x48000000))

// bank configure registers
#define	R_BANKCON6	(*((volatile unsigned long *)0x4800001c))

// REFRESH CONTROL REGISTER(REFRESH)
#define	R_REFRESH	(*((volatile unsigned long *)0x48000024))

// BANKSIZE REGISTER(BANKSIZE)
#define	R_BANKSIZE	(*((volatile unsigned long *)0x48000028))

/************************* SDRAM Registers ********************/
// SDRAM MODE REGISTER SET REGISTER (MRSR)
#define	R_MRSRB6	(*((volatile unsigned long *)0x4800002c))
/**************************************************************/

/************************* NAND FLASH Registers ***************/
// NAND FLASH CONFIGURATION REGISTER(NFCONF)
#define	R_NFCONF	(*((volatile unsigned long *)0x4e000000))
// CONTROL REGISTER
#define	R_NFCONT	(*((volatile unsigned long *)0x4e000004))
// COMMAND REGISTER
#define	R_NFCMMD	(*((volatile unsigned long *)0x4e000008))
// DATA REGISTER
#define	R_NFDATA	(*((volatile unsigned long *)0x4e000010))
// ADDRESS REGISTER
#define	R_NFADDR	(*((volatile unsigned long *)0x4e00000c))
// NFCON STATUS REGISTER
#define	R_NFSTAT	(*((volatile unsigned long *)0x4e000020))
/**************************************************************/

#endif /* BOOT_H */
